#1 eFPGA: most customers, tapeouts, nodes, sizes, options, metal stacks

What is eFPGA

Embedded FPGA (Field Programmable Gate Array,) or eFPGA, is a way to instantiate FPGA flexibility inside the SoC without the burden of external FPGA overhead.  eFPGA enables your SoC to have flexibility in critical areas where algorithm, protocol or market requirements are changing.

By adding eFPGA, SoCs get reconfigurable computing so products can service different markets and extend the life of SoCs as well as reduce latency, save power and cost.  eFPGA can also accelerate many workloads faster than processors.  When adding eFPGA close to the processor, heavy software workloads can be offloaded to reconfigurable eFPGA hardware resulting in 1000x speed increase and allowing the processor to be ready for urgent requests.  This can be critical for security or safety applications.

Flex Logix provides eFPGA cores which have density and performance similar to leading FPGAs in the same process node but only use standard cells. Our EFLX eFPGA is silicon proven in 180nm, 40nm, 28/22nm, 16nm and 12nm with 6/7nm EFLX eFPGA is in design and 5nm next.

The magic in FPGAs is the interconnect network that allows any logic block to connect to any other – this is also programmable.  Traditional FPGAs use 2D-mesh architectures that require 10+ metal layers and take up much more area than the logic blocks themselves.  Typically, in a traditional FPGA the interconnect uses ~80% of the area of the “fabric” (the programmable part of the FPGA consisting of programmable logic and programmable interconnect).  

Flex Logix uses a new, patented interconnect, XFLX™(the subject of the Outstanding Paper award at ISSCC 2014), which uses about half the area of the traditional interconnect and uses only 5-7 metal routing layers, but with very high utilization (typically over 90%.)  Since we use few metal layers our IP is compatible with almost all metal stacks. 

At first glance, it  XFLX looks like a hierarchical network that has been tried before, but it incorporates numerous improvements to improve spacial locality so as to cut area and reduce metal layers while at the same time maintaining performance.  The paper presented at ISSCC is copyrighted so please refer to the 2014 ISSCC proceedings for more detail.  The XFLX interconnect has evolved and improvements are covered by several additional US patents.

Our eFPGA is based on a “tile” called EFLX 4K, which comes in two versions: all logic or mostly logic with some MACs (multiply-accumulators). The programmable logic is called LUTs (lookup tables) that can implement any Boolean function. EFLX 4K Logix has 4000 LUT4 equivalents, EFLX 4K DSP has 3000 LUT4s and 40 Multiplier-Accumulators (MACs): the MAC has a 22-bit pre-adder, a 22×22 multiple and a 48-bit post adder/accumulator.  MACs can be combined or cascaded to form fast DSP functions.  We can build an eFPGA array of tiles of any combination to match the requirement of the SoC (for 40nm-180nm we offer an EFLX 1K tile for smaller arrays).

The EFLX 4K tiles also have an interconnect called ArrayLinx™ which connects tiles into arrays with a mesh interconnect. ArrayLinx allows interconnections between tiles. The XFLX interconnect in each tile connects up to the ArrayLinx. The two types of cores can be mixed in arrays up to 500K LUT4s, with a roadmap to >2M LUT4s.

More information on the structure and pipelining of DSP MACs is available HERE.

In FPGA chips, RAM is spread throughout the array. This is possible with EFLX as well: using RAMLinx™ interconnect, RAMs on any kind and size can be integrated between rows or columns of an EFLX array. 

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